ABSTRACT: Advanced semiconductor packaging is playing a crucial role in enhancing system performance and functionality. As computing demands continue to rise, particularly in emerging technologies, heterogeneous three-dimensional (3D) integration system with fine-pitch, high-density interconnections, and multi-chip stacks offers significant promise for the future. 3D metal interconnects, such as through-silicon vias (TSVs), through-glass vias (TGVs), hybrid bonding and micro bumps, have enabled the development of several generations of high-bandwidth memory (HBM), which is critical for high-end computation applications, including graphics accelerators, network devices, datacenter AI ASICs, and FPGAs. For next-generation semiconductor packaging and heterogeneous systems, advanced semiconductor metal interconnect technologies will be essential for achieving ultra-high 3D interconnect densities. However, the aggressive scaling of interconnect pitches and the use of nanoscale interconnect materials present significant challenges in process development, along with reliability issues related to thermal processing and annealing conditions (200°C–400°C). Additionally, these high-density 3D integration systems lead to significant increases in heat flux and power density (500-1000 W/cm²), resulting in thermal crosstalk, hotspots, and thermal- mechanical stress, all of which contribute to serious thermal-related reliability concerns. Effective, energy-efficient thermal management solutions are critical to addressing those thermal challenges. In this presentation, I will address two critical thermal challenges in next-generation 3D heterogeneous integration systems: (1) Thermal/Mechanical Reliability of 3D Metal Interconnect Materials Under Thermal Annealing Conditions, where I will share our latest research on thermal behavior, mechanical stress, and microstructure evolution during the scaling of 3D interconnect materials, as well as novel materials for vertical 3D interconnects; and (2) Efficient Thermal Management: Cooling Semiconductor 3D Chips/Packaging from Exterior to Core, which involves examining thermal transport phenomena across various levels, from device-interconnect level to chip and packaging level. Additionally, I will present our recent achievement in direct-on-chip package-level single-phase and two-phase microfluidic cooling, near-junction cooling techniques, and the chip/package integration of innovative thermal packaging materials optimized for superior heat spreading and extreme thermal isolation.

BIO: Dr. Tiwei Wei (Senior Member, IEEE) is an Assistant Professor in the School of Mechanical Engineering at Purdue University. He completed postdoctoral research at Stanford University's NanoHeat Lab (2020–2022) and earned his Ph.D. in 2020 in Applied Mechanics and Energy Conversion (TME), along with the 3D System Integration program at the Interuniversity Microelectronics Centre (imec) and KU Leuven in Belgium. Prior to this, he held senior research positions at Tsinghua University and HKUST (2011–2015), focusing on advanced semiconductor packaging manufacturing and thermal packaging integration. His current research interests include semiconductor packaging, heterogeneous 3D integration, thermal management, and electronic cooling. Dr. Wei has published over 60 papers and holds more than 10 patents. He previously served as the vice-chair of the IEEE EPS Silicon Valley Chapter and is currently the chair of the IEEE EPS Central Indiana Chapter. Additionally, he chaired the 2024 IEEE Symposium on Reliability for Electronics and Photonics Packaging (REPP). His research in semiconductor packaging manufacturing and thermal packaging has been recognized with numerous awards, including the 2024 Intel Rising Star Faculty Award, the 2024 Purdue Seed for Success Acorn Award, the 2020 IMEC Ph.D. Excellence Award, the 2012 IEEE ICEPT Outstanding Paper Award, and multiple best presentation awards at conferences such as IEEE ITherm, IEEE REPP, and IEEE ECTC.